1. Field of the Invention
The present invention generally relates to address snoop methods and multi-processor systems, and more particularly to an address snoop method for carrying out an address snoop process in a multi-processor system in which a plurality of processor blocks are coupled to a plurality of input and output (I/O) blocks via a connecting apparatus, and to a multi-processor system which employs such an address snoop method.
2. Description of the Related Art
A multi-processor system has a structure in which a plurality of processor blocks and a plurality of I/O blocks are coupled via a connecting apparatus also referred to as data and address crossbars. Each processor block includes a plurality of processors and a plurality of memories. On the other hand, each I/O block includes a storage unit such as a disk drive. In the following description, it will be assumed for the sake of convenience that each processor block is formed by a CPU block that has a plurality of CPUs and a plurality of cache memories.
In the conventional multi-processor system, the I/O block is provided in a 1:1 relationship to the CPU block or, even, if a plurality of I/O blocks are independent, a small number of I/O blocks can be shared by a plurality of CPU blocks. However, the number of accesses among the cache memories increases proportionally to the number of CPU blocks, and increasing the number of CPU blocks does not necessarily improve the performance of the multi-processor system. Accordingly, a system has been proposed to improve the performance of the multi-processor system by interconnecting the CPU blocks via the I/O blocks.
However, even when such a proposed system is employed, if the number of I/O blocks per CPU block is in a 1:1 ratio as in the case of the conventional multi-processor system or, the I/O blocks are shared by a plurality of CPU blocks, the performance of the multi-processor system is greatly restricted, thereby eliminating the significance of employing such a proposed system.
For this reason, there are demands to realize a structure which can implement a large number of I/O blocks, increase the number of I/O blocks usable by each CPU block, and use the CPU blocks and the I/O blocks in a flexible combination.
For example, a Japanese Laid-Open Patent Application No. 9-138782 proposes a multi-processor system having a structure in which a memory access output by a processor unit is monitored by other cache memories using the interconnected network. On the other hand, Japanese Laid-Open Patent Application No. 9-138783 proposes a multi-processor system having a mechanism that simultaneously executes a plurality of unicastings having different transfer destination ports. In addition, Japanese Laid-Open Patent Application No. 2001-184321 proposes a multi-processor system coupled via a node interconnecting network.
When a large number of I/O blocks are implemented in the multi-processor system, independently of the CPU blocks and the CPU blocks and the I/O block communicable connect by data and address crossbars, it becomes necessary to separately snoop the address in each I/O block. In other words, conventionally each I/O block includes address snoop circuitry and/or programmable logic. In this case, it is necessary to supply a signal required for an address snoop process from the address connecting apparatus (or address crossbar) to each I/O block. However, in order to supply the signal required for the address snoop process to each I/O block, it is necessary to take implementation measures, such as increasing the number of pins of the address connecting apparatus per LSI and dividing the functions of a plurality of LSIs, thereby introducing problems in that the implementation is difficult and that the cost increases. In addition, because of the structure of the multi-processor system (particularly the address connecting apparatus and the I/O blocks), a wiring length increases and a transmission delay is generated, thereby introducing a problem in that the upper limit of the performance of the multi-processor system deteriorates (latency increases).